This invention relates generally to semiconductor devices, and more particularly to the fabrication of monolithic circuits having matched complementary bipolar transistors, with one polarity type transistor having self-isolating characteristics and the other polarity type being selectively isolated from other circuit elements by circumscribing P-N junction isolation regions.
In the fabrication of complete functional circuits in monolithic form, both NPN and PNP transistors and semiconductor diodes, capacitors, and resistors can be formed on the same semiconductor substrate by various combinations of the same diffusion steps. Since yields tend to decrease exponentially with an increase in the number of diffusion steps in any particular fabrication process, it is advantageous to minimize the diffusion steps required to form the circuit components. If an integrated circuit uses only one type of transistor, only three diffusions are typically used, whereas if both NPN and PNP transistors, as well as other semiconductor devices, are required for the circuit, it is generally necessary to make at least four diffusions. A number of techniques have been devised which utilize an even larger number of diffusion steps, particularly when the NPN and PNP transistors must have matched operational parameters.
The prior art is replete with processes and techniques utilized to produce monolithic integrated circuits having both PNP and NPN transistors on the same substrate. In one known process, the PNP transistors are formed by utilizing the base and collector diffusions of the NPN transistors and the p-type substrate. However, the use of the same diffusion to form different components must necessarily result in the trade off of desirable operational parameters between the NPN and PNP devices. As a general rule, when a p-type substrate is used, the PNP transistor is of low quality and when an n-type substrate is used, the NPN device is of low quality. In other known processes of this type, additional diffusion cycles are used to improve the electrical characteristics of the PNP transistor. Some of these prior known processes and techniques are described in a publication entitled "Designing A Micro Electronic Differential Amplifier", Electron Products, pages 34-37, July, 1962; and in a publication entitled "Low Power Integrated Circuits", Westcon Electronics Show and Convention, 1965,; Session 1; and in a publication entitled "Lateral Complementary Transistor Structure for the Simultaneous Fabrication of Functional Blocks", Proceedings of the IEEE, Pages 1491-1495, December, 1964.
Another known example of a monolithic integrated circuit having complementary transistors formed therein can be found in U.S. Pat. No. 3,327,182 entitled "Semiconductor Integrated Circuit Structure and Method of Making the Same" issued to Paul M. Kisinko on June 20, 1967. This patent discloses a technique for fabricating a structure that includes transistors of both polarities of which one is formed by triple diffusion but with an impurity concentration gradient in the collector region that is a maximum away from the base collector junction so that the base-collector junction break down voltage is increased typically to about 65 volts. In accordance with this patent, the collector region of the triple diffused transistor is formed by deposition of doping impurity material between epitaxially grown layers. Upon redistribution the diffused collector extends through the epitaxial layers and has its maximum impurity concentration away from the surface. Consequently, the impurity concentration in subsequently diffused operations need not be as high as in normal triple diffused structures and break down voltage is greater.
Other examples of known processes for producing monolithic integrated circuits having matched complementary transistors in the same semiconductor substrate can be found in U.S. Pat. No. 3,465,215, entitled "Process for Fabricating Monolithic Circuits Having Matched Complementary Transistors and Product", issued Sept. 2, 1969, to R. O. Bohannon, Jr. et al, and U.S. Pat. No. 3,474,309, entitled "Monolithic Circuit with High Q Capacitor", issued Oct. 21, 1969 to R. A. Stehlin, each assigned to the assignee of this application.
In general, the prior art processes and techniques for producing complementary transistors on a single substrate have yielded complementary transistors having characteristics that are satisfactory in many respects, but such processes are so complex as to not be suitable for mass production operations. In production runs the yields of good devices tend to decrease with the number of diffusion steps involved in the process.
In accordance with the fundamental objectives of this invention, a relatively simple process involving six diffusions, the first of which is non- critical, produces a monolithic integrated circuit having both NPN and PNP transistors with closely matched parameters of high values. In addition, all electrical components are electrically isolated from other electrical components.
In accordance with the present invention, a process for fabricating monolithic integrated circuits having matched complementary transistors is provided that includes the steps of diffusing a plurality of first regions of one conductivity type into a starting material of opposite conductivity type; selectively depositing impurity concentration second regions of the opposite conductivity type into some of the first regions and selectively circumscribing the remaining first regions; epitaxially depositing a material of the one conductivity type thereover and then to up-diffuse the second regions through the epitaxial layer until they surface to produce regions of the opposite conductivity type that have retrograded impurity concentration profiles. The retrograded second regions that extend from the first regions function as collector regions for the PNP transistors and are surrounded by material of the one conductivity type so as to provide self isolation for any semiconductor device formed therein; whereas the retrograded second regions that circumscribe the first regions function as diffused isolation regions to provide electrical isolation for any semiconductor device formed within such isolation regions from other circuit elements. Base and emitter regions may then be diffused into the retrograded second regions that extend from the first regions, and into the epitaxial material circumscribed by the retrograded isolation regions, to produce a monolithic integrated circuit having matched complementary transistors.
It is therefore one object of the present invention to provide a process for fabricating monolithic integrated circuits having matched complementary semiconductor devices of improved performance characteristics and control ability.
Another object of this invention is to provide a monolithic integrated circuit having matched complementary semiconductor devices in which up- diffused regions having retrograded impurity concentration profiles forming the collector regions for the transistors of one polarity type to produce self isolation capability.
Another object of this invention is to provide a monolithic integrated circuit having matched complementary semiconductor devices in which up-diffused regions having retrograded impurity concentrated profiles circumscribe the collector regions for transistors of one polarity type for electrically isolating such transistors from other circuit components.
Another object of this invention is to provide a monolithic integrated circuit having matched complementary semiconductor devices that is substantially simple in design and relatively inexpensive to manufacture.
These and other objects and features of this invention will readily be apparent from the following detailed description when taken in conjunction with the appended claims and attached drawings.